# Design Examples

In this course, digital design concepts and SystemVerilog features will be introduced through examples of gradually increasing complexity, inspired by real digital systems, as follows:

| # | Design | File List | RTL | TB | Sim & GDS |
|---|---|---|---|---|---|
| 1 | Not Gate | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/1_not_gate.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/not_gate.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_not_gate.sv) | [link](not-gate) |
| 2 | Full Adder | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/2_full_adder.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/full_adder.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_full_adder.sv) | [link](full-adder) |
| 3 | N-Adder | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/3_n_adder.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/n_adder.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_n_adder.sv) | [link](n-adder) |
| 4 | ALU | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/4_alu.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/alu.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_alu.sv) | [link](alu) |
| 5 | Encoder | — | — | — | — |
| 6 | Decoder | — | — | — | — |
| 7 | Verilog Functions | — | — | — | — |
| 8 | Flip Flop | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/8_flip_flop.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/flip_flop.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_flip_flop.sv) | [link](flip-flop) |
| 9 | Up counter | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/9_up_counter.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/up_counter.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_up_counter.sv) | [link](up-counter) |
| 10 | Binary Reduction Tree | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/18_reduction_tree_min.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/reduction_tree_min.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_reduction_tree_min.sv) | [link](reduction-tree-min) |
| 11 | Parallel to Serial Converter | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/11_parallel_to_serial.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/parallel_to_serial.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_parallel_to_serial.sv) | [link](parallel-to-serial) |
| 12 | Down counter | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/12_down_counter.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/down_counter.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_down_counter.sv) | [link](down-counter) |
| 13 | UART RX | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/13_uart_rx.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/uart_rx.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_uart_rx.sv) | [link](uart-rx) |
| 14 | UART TX | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/14_uart_tx.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/uart_tx.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_uart_tx.sv) | [link](uart-tx) |
| 15 | UART Echo (RX + TX) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/15_uart_echo.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/uart_echo.v) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_uart_echo.sv) | [link](uart-echo) |
| 16 | FIR Filter [Retimed RTL](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/fir_filter_retimed.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/16_fir_filter.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/fir_filter.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_fir_filter.sv) | [link](fir-filter) |
| 17 | UART RX + TX + FIR Filter | [link](https://github.com/abarajithan11/digital-design/blob/main/material/designs/17_sys_fir_filter.f) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/rtl/sys_fir_filter.sv) | [link](https://github.com/abarajithan11/digital-design/blob/main/material/tb/tb_sys_fir_filter.sv) | [link](sys-fir-filter) |

## Waveforms and ASAP7 GDS

For each design our GitHub Actions flow runs

1. Simulation using Verilator, generating VCD, converted to SVG,
2. OpenROAD RTL2GDS2 flow using [ASAP7 7nm, a realistic PDK for academic use,](https://www.sciencedirect.com/science/article/pii/S002626921630026X)

collects their outputs and displays them here. 

To reproduce this on your machine, check out our [docker setup](setting-up-docker.md).

* Our repository: [github.com/abarajithan11/digital-design](https://github.com/abarajithan11/digital-design)
* Filelists: [material/designs](https://github.com/abarajithan11/digital-design/tree/main/material/designs)
* SystemVerilog RTL: [material/rtl](https://github.com/abarajithan11/digital-design/tree/main/material/rtl)
* Testbenches: [material/tb](https://github.com/abarajithan11/digital-design/tree/main/material/tb)
* Makefile: [material/Makefile](https://github.com/abarajithan11/digital-design/tree/main/material/Makefile)
* OpenRoad Flow: [material/openroad](https://github.com/abarajithan11/digital-design/tree/main/material/openroad)

## 1. Not Gate

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/1_not_gate/1_not_gate.vcd), [Full SVG](_static/design-outputs/1_not_gate/1_not_gate_full.svg), [GDS](_static/design-outputs/1_not_gate/1_not_gate.gds), [GDS Logs](_static/design-outputs/1_not_gate/logs.zip)

**Waveform (0-10 ns)**


![1_not_gate waveform](_static/design-outputs/1_not_gate/1_not_gate_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/1_not_gate/final_routing.webp" alt="1_not_gate routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/1_not_gate/final_placement.webp" alt="1_not_gate placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/1_not_gate/final_worst_path.webp" alt="1_not_gate worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 2. Full Adder

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/2_full_adder/2_full_adder.vcd), [Full SVG](_static/design-outputs/2_full_adder/2_full_adder_full.svg), [GDS](_static/design-outputs/2_full_adder/2_full_adder.gds), [GDS Logs](_static/design-outputs/2_full_adder/logs.zip)

**Waveform (0-10 ns)**


![2_full_adder waveform](_static/design-outputs/2_full_adder/2_full_adder_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/2_full_adder/final_routing.webp" alt="2_full_adder routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/2_full_adder/final_placement.webp" alt="2_full_adder placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/2_full_adder/final_worst_path.webp" alt="2_full_adder worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 3. N Adder

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/3_n_adder/3_n_adder.vcd), [Full SVG](_static/design-outputs/3_n_adder/3_n_adder_full.svg), [GDS](_static/design-outputs/3_n_adder/3_n_adder.gds), [GDS Logs](_static/design-outputs/3_n_adder/logs.zip)

**Waveform (0-10 ns)**


![3_n_adder waveform](_static/design-outputs/3_n_adder/3_n_adder_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/3_n_adder/final_routing.webp" alt="3_n_adder routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/3_n_adder/final_placement.webp" alt="3_n_adder placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/3_n_adder/final_worst_path.webp" alt="3_n_adder worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 4. Alu

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/4_alu/4_alu.vcd), [Full SVG](_static/design-outputs/4_alu/4_alu_full.svg), [GDS](_static/design-outputs/4_alu/4_alu.gds), [GDS Logs](_static/design-outputs/4_alu/logs.zip)

**Waveform (0-10 ns)**


![4_alu waveform](_static/design-outputs/4_alu/4_alu_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/4_alu/final_routing.webp" alt="4_alu routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/4_alu/final_placement.webp" alt="4_alu placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/4_alu/final_worst_path.webp" alt="4_alu worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 8. Flip Flop

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/8_flip_flop/8_flip_flop.vcd), [Full SVG](_static/design-outputs/8_flip_flop/8_flip_flop_full.svg), [GDS](_static/design-outputs/8_flip_flop/8_flip_flop.gds), [GDS Logs](_static/design-outputs/8_flip_flop/logs.zip)

**Waveform (0-10 ns)**


![8_flip_flop waveform](_static/design-outputs/8_flip_flop/8_flip_flop_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/8_flip_flop/final_routing.webp" alt="8_flip_flop routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/8_flip_flop/final_placement.webp" alt="8_flip_flop placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/8_flip_flop/final_worst_path.webp" alt="8_flip_flop worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 9. Up Counter

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/9_up_counter/9_up_counter.vcd), [Full SVG](_static/design-outputs/9_up_counter/9_up_counter_full.svg), [GDS](_static/design-outputs/9_up_counter/9_up_counter.gds), [GDS Logs](_static/design-outputs/9_up_counter/logs.zip)

**Waveform (0-10 ns)**


![9_up_counter waveform](_static/design-outputs/9_up_counter/9_up_counter_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/9_up_counter/final_routing.webp" alt="9_up_counter routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/9_up_counter/final_placement.webp" alt="9_up_counter placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/9_up_counter/final_worst_path.webp" alt="9_up_counter worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 10. Reduction Tree Min

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/10_reduction_tree_min/10_reduction_tree_min.vcd), [Full SVG](_static/design-outputs/10_reduction_tree_min/10_reduction_tree_min_full.svg), [GDS](_static/design-outputs/10_reduction_tree_min/10_reduction_tree_min.gds), [GDS Logs](_static/design-outputs/10_reduction_tree_min/logs.zip)

**Waveform (0-10 ns)**


![10_reduction_tree_min waveform](_static/design-outputs/10_reduction_tree_min/10_reduction_tree_min_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/10_reduction_tree_min/final_routing.webp" alt="10_reduction_tree_min routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/10_reduction_tree_min/final_placement.webp" alt="10_reduction_tree_min placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/10_reduction_tree_min/final_worst_path.webp" alt="10_reduction_tree_min worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 11. Parallel To Serial

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/11_parallel_to_serial/11_parallel_to_serial.vcd), [Full SVG](_static/design-outputs/11_parallel_to_serial/11_parallel_to_serial_full.svg), [GDS](_static/design-outputs/11_parallel_to_serial/11_parallel_to_serial.gds), [GDS Logs](_static/design-outputs/11_parallel_to_serial/logs.zip)

**Waveform (0-10 ns)**


![11_parallel_to_serial waveform](_static/design-outputs/11_parallel_to_serial/11_parallel_to_serial_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/11_parallel_to_serial/final_routing.webp" alt="11_parallel_to_serial routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/11_parallel_to_serial/final_placement.webp" alt="11_parallel_to_serial placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/11_parallel_to_serial/final_worst_path.webp" alt="11_parallel_to_serial worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 12. Down Counter

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/12_down_counter/12_down_counter.vcd), [Full SVG](_static/design-outputs/12_down_counter/12_down_counter_full.svg), [GDS](_static/design-outputs/12_down_counter/12_down_counter.gds), [GDS Logs](_static/design-outputs/12_down_counter/logs.zip)

**Waveform (0-10 ns)**


![12_down_counter waveform](_static/design-outputs/12_down_counter/12_down_counter_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/12_down_counter/final_routing.webp" alt="12_down_counter routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/12_down_counter/final_placement.webp" alt="12_down_counter placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/12_down_counter/final_worst_path.webp" alt="12_down_counter worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 13. Uart Rx

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/13_uart_rx/13_uart_rx.vcd), [Full SVG](_static/design-outputs/13_uart_rx/13_uart_rx_full.svg), [GDS](_static/design-outputs/13_uart_rx/13_uart_rx.gds), [GDS Logs](_static/design-outputs/13_uart_rx/logs.zip)

**Waveform (0-10 ns)**


![13_uart_rx waveform](_static/design-outputs/13_uart_rx/13_uart_rx_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/13_uart_rx/final_routing.webp" alt="13_uart_rx routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/13_uart_rx/final_placement.webp" alt="13_uart_rx placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/13_uart_rx/final_worst_path.webp" alt="13_uart_rx worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 14. Uart Tx

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/14_uart_tx/14_uart_tx.vcd), [Full SVG](_static/design-outputs/14_uart_tx/14_uart_tx_full.svg), [GDS](_static/design-outputs/14_uart_tx/14_uart_tx.gds), [GDS Logs](_static/design-outputs/14_uart_tx/logs.zip)

**Waveform (0-10 ns)**


![14_uart_tx waveform](_static/design-outputs/14_uart_tx/14_uart_tx_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/14_uart_tx/final_routing.webp" alt="14_uart_tx routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/14_uart_tx/final_placement.webp" alt="14_uart_tx placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/14_uart_tx/final_worst_path.webp" alt="14_uart_tx worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 15. Uart Echo

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/15_uart_echo/15_uart_echo.vcd), [Full SVG](_static/design-outputs/15_uart_echo/15_uart_echo_full.svg), [GDS](_static/design-outputs/15_uart_echo/15_uart_echo.gds), [GDS Logs](_static/design-outputs/15_uart_echo/logs.zip)

**Waveform (0-10 ns)**


![15_uart_echo waveform](_static/design-outputs/15_uart_echo/15_uart_echo_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/15_uart_echo/final_routing.webp" alt="15_uart_echo routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/15_uart_echo/final_placement.webp" alt="15_uart_echo placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/15_uart_echo/final_worst_path.webp" alt="15_uart_echo worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 16. Fir Filter

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/16_fir_filter/16_fir_filter.vcd), [Full SVG](_static/design-outputs/16_fir_filter/16_fir_filter_full.svg), [GDS](_static/design-outputs/16_fir_filter/16_fir_filter.gds), [GDS Logs](_static/design-outputs/16_fir_filter/logs.zip)

**Waveform (0-10 ns)**


![16_fir_filter waveform](_static/design-outputs/16_fir_filter/16_fir_filter_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/16_fir_filter/final_routing.webp" alt="16_fir_filter routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/16_fir_filter/final_placement.webp" alt="16_fir_filter placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/16_fir_filter/final_worst_path.webp" alt="16_fir_filter worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>

## 17. Sys Fir Filter

**Run results**

- Simulation: passed, RTL2GDS: passed
- Artifacts : [VCD](_static/design-outputs/17_sys_fir_filter/17_sys_fir_filter.vcd), [Full SVG](_static/design-outputs/17_sys_fir_filter/17_sys_fir_filter_full.svg), [GDS](_static/design-outputs/17_sys_fir_filter/17_sys_fir_filter.gds), [GDS Logs](_static/design-outputs/17_sys_fir_filter/logs.zip)

**Waveform (0-10 ns)**


![17_sys_fir_filter waveform](_static/design-outputs/17_sys_fir_filter/17_sys_fir_filter_short.svg)

**Layout Reports**

<div style="display:grid; grid-template-columns:repeat(auto-fit,minmax(220px,1fr)); gap:12px; max-width:1100px; margin:0 auto;">
  <img src="_static/design-outputs/17_sys_fir_filter/final_routing.webp" alt="17_sys_fir_filter routing" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/17_sys_fir_filter/final_placement.webp" alt="17_sys_fir_filter placement" style="width:100%; height:auto; display:block;" />
  <img src="_static/design-outputs/17_sys_fir_filter/final_worst_path.webp" alt="17_sys_fir_filter worst path" style="width:100%; height:auto; display:block;" />
</div>
<p style="text-align:center;">Routing, Placement, Worst path</p>