# Standard Cells in 3D This page shows 3D visualizations of standard cells used by four different open source PDKs (ASAP7, nangate45, Skywater130, and Skywater130 High Density). Standard cells are the building blocks that the EDA software puts together to make a chip layout out of the SytemVerilog design you write. The following are selected standard cells in the 7nm ASAP7 PDK. You can drag to rotate and scroll to zoom. To generate them from our Docker container, run: ```bash make show_3d_cell # show all available cells make show_3d_cell CELL=NAND2x1 # show NAND2x1 ``` ```{raw} html

NOT gate standard cell in ASAP7 — NOT gate (INVx1)

NAND gate standard cell in ASAP7 — NAND gate (NAND2x1)

And-or-invert standard cell in ASAP7 — AND-OR-INVERT (AOI211x1)

D flip-flop standard cell in ASAP7 — D Flip-Flop (DFFHQNx1)

``` ## ASAP7 ```{raw} html

Choose a cell to view in 3D

``` ## NanGate45 ```{raw} html

Choose a cell to view in 3D

``` ## Sky130 ```{raw} html

Choose a cell to view in 3D

``` ## Sky130HD ```{raw} html

Choose a cell to view in 3D

```