My Work Reusable AXI-stream verification IPs in SystemVerilog March 16, 2026 A Framework to Evaluate Verification Methods by Automatically Injecting Bugs into SoC IPs March 16, 2026 FireBridge: Verifying SoC Subsystems with Real Firmware Without Simulating a CPU March 16, 2026 CocoTB: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub April 4, 2022 Neural Chip Design [4/4: SoC Integration & Firmware] January 29, 2022 Neural Chip Design [3/4: RTL Design & Verification] January 29, 2022 Neural Chip Design [2/4: Golden Model] January 29, 2022 Neural Chip Design [1/4: Overview] January 28, 2022 Vision-Based Adaptive Traffic Control on an MPSoC [ARM+FPGA] January 28, 2022 SOC Design to Apply Two 7x7 Kernels to a 1080p YUV Video Feed at 30 FPS October 19, 2019 Serial System Bus + Protocol May 18, 2019 Smart Lock: Assembly Programming, Product Realization, Marketing July 18, 2018 Custom Processor (Verilog), ISA, Compiler & Simulator (Python) June 17, 2018 Gollum - Ring Finding Robot: [GPS, obstacle avoiding, wall following, color detection, parallel alignment] August 27, 2017 Dobbybot: A Battlebot under $32 July 18, 2016