G Abarajithan

PhD student @ UC San Diego; SoC Integration; Hardware Security & Verification; RTL for Edge AI

I am a PhD student in Kastner Research Lab @ UCSD CSE, focusing on hardware security and verification, building robust hardware/software co-designs, and accelerating AI/ML at the edge. Welcome to my personal blog, where I document my technical explorations, projects, and thoughts.

Tech Stack

  • Languages: SystemVerilog (RTL, DV, SVA), Python, C/C++, Bash, Tcl
  • EDA Tools: AMD/Xilinx Vivado, Cadence Genus, Cadence Innovus, Synopsys Design Compiler
  • Verification: Verilator, VCS, Xsim, Questa Formal, SymbiYosys, cocotb
  • Other: Git, Docker, LaTeX, GitHub Actions

Projects

  • SoC Fuzzing Benchmark: A standardized testbed to evaluate hardware fuzzers like Intel PreSiFuzz and RFuzz. Maps their bytestreams into AXI and test them on SoC IPs with automatically injected bugs. [more…]

  • CGRA4ML: An open-source framework for scientific edge computing that maps DNNs from Python to custom, parameterizable SystemVerilog CGRAs with C firmware with FPGA and ASIC flows. [more…]

  • FireBridge: A framework to enable rapid Firmware/Hardware co-development at the system-level. Bridges SystemVerilog AXI subsystems to real C firmware via DPI-C, without simulating a CPU. [more…]

  • SystemVerilog Course for 300 students: 64-hour short course, collaborating with Synopsys, covering RTL design, randomized transactional testbenches, AXI protocol design, FPGA & ASIC flow labs. [more…]

  • Lightweight Formal AXI VIP: A reusable Formal VIP for AXI4 and AXI5 protocols and for complex IPs like interconnects being built and tested against both open-source and commercial tools. [more…]

  • AXI Stream Systolic Array: A lightweight, highly parameterizable systolic array in SV, integrated with Ibex-SoC via AXI DMAs, a custom DMA controller, and corresponding C firmware. Currently being formally verified. [more…]

  • Course projects: Complete UVM Testbench in 580 lines, A Rust-based Compiler for a Custom Functional Language to x86

Publications

  • CGRA4ML: A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing. G Abarajithan, Z Ma, R Munasinghe, F Restuccia, R Kastner. ACM Transactions on Reconfigurable Technology and Systems, 2026/2024. [link]
  • Within-Camera Multilayer Perceptron DVS Denoising. A Rios-Navarro, S Guo, G Abarajithan, K Vijayakumar, et al. Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2023. [link]
  • Kraken: An Efficient Engine with a Uniform Dataflow for Deep Neural Networks. G Abarajithan, CUS Edussooriya. arXiv preprint arXiv:2112.02793, 2021. [link]

Contact Me