G Abarajithan

G Abarajithan

PhD student @ UC San Diego working on Hardware Security & Verification, Custom Hardware for Edge AI and SoC-level Integration

SoC

CGRA4ML: An End-to-End Framework for Deploying DNNs on FPGAs and ASICs

CGRA4ML: An End-to-End Framework for Deploying DNNs on FPGAs and ASICs

Lightweight Formal AXI VIP

Lightweight Formal AXI VIP

SystemVerilog Course at Scale

SystemVerilog Course at Scale

A Framework to Evaluate Verification Methods by Automatically Injecting Bugs into SoC IPs

A Framework to Evaluate Verification Methods by Automatically Injecting Bugs into SoC IPs

AXI-Stream Systolic Array → SoC Testbed

AXI-Stream Systolic Array → SoC Testbed

December 10, 2025

CocoTB: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub

CocoTB: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub

Vision-Based Adaptive Traffic Control on an MPSoC [ARM+FPGA]

Vision-Based Adaptive Traffic Control on an MPSoC [ARM+FPGA]

January 28, 2022

Serial System Bus + Protocol

Serial System Bus + Protocol