Projects CGRA4ML: Py+SV+C Framework for DNNs → FPGA/ASIC March 16, 2026 Lightweight Formal AXI VIP March 16, 2026 SystemVerilog Course at Scale March 15, 2026 Hardware Fuzzing Benchmark Framework for AXI March 10, 2026 AXI-Stream Systolic Array → SoC Testbed December 10, 2025 AI Engine Experiments October 25, 2025 FireBridge: Verifying SoC Subsystems with Real Firmware Without Simulating a CPU October 16, 2025 Reusable AXI-stream verification IPs in SystemVerilog May 16, 2025 CocoTB: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub April 4, 2022 Vision-Based Adaptive Traffic Control on an MPSoC [ARM+FPGA] January 28, 2022 Serial System Bus + Protocol May 18, 2019 CSIRO: End-to-End Machine Learning Pipeline December 17, 2018 In May 2018, I was chosen for a 6 month paid internship program at DATA61 CSIRO (The national science agency of Australia), in Brisbane, ... Custom Processor (Verilog), ISA, Compiler & Simulator (Python) June 17, 2018 The first architecture I designed
![Vision-Based Adaptive Traffic Control on an MPSoC [ARM+FPGA]](https://media.abapages.com/content/images/2021/11/IMG_20191204_112837--1--1.jpg)
