AXI CGRA4ML: Py+SV+C Framework for DNNs → FPGA/ASIC March 16, 2026 Lightweight Formal AXI VIP March 16, 2026 SystemVerilog Course at Scale March 15, 2026 Hardware Fuzzing Benchmark Framework for AXI March 10, 2026 AXI-Stream Systolic Array → SoC Testbed December 10, 2025 FireBridge: Verifying SoC Subsystems with Real Firmware Without Simulating a CPU October 16, 2025 Reusable AXI-stream verification IPs in SystemVerilog May 16, 2025
