Design Examples

In this course, digital design concepts and SystemVerilog features will be introduced through examples of gradually increasing complexity, inspired by real digital systems, as follows:

#	Design	Files	RTL	TB	Results
1	1-bit Full Adder	link	link	link	link
2	N-bit Ripple Carry Adder	link	link	link	link
3	ALU	link	link	link	link
4	Up Counter	link	link	link	link
5	Binary Reduction Tree	link	link	link	link
6	AXI-Stream Parallel to Serial Converter	link	link	link	link
7	Down Counter (Chainable)	link	link	link	link
8	UART RX	link	link	link	link
9	UART TX	link	link	link	link
10	UART Echo (RX + TX) System	link	link	link	link
11	FIR Filter [Naive RTL]	link	link	link	link
12	System: 100-tap FIR Filter via UART [Python filter]	link	link	link	link

Waveforms and ASAP7 GDS

For each design our GitHub Actions flow runs

1. Simulation using Verilator, generating VCD, converted to SVG,

2. OpenROAD RTL2GDS2 flow using ASAP7 7nm, a realistic PDK for academic use,

collects their outputs and displays them here.

To reproduce this on your machine, check out our docker setup.

• Our repository: github.com/abarajithan11/digital-design

• Filelists: material/designs

• SystemVerilog RTL: material/rtl

• Testbenches: material/tb

• Makefile: material/Makefile

• OpenRoad Flow: material/openroad

1. 1-bit Full Adder

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

full_adder waveform

2. N-bit Ripple Carry Adder

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

n_adder waveform

3. ALU

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

alu waveform

4. Up Counter

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

up_counter waveform

5. Binary Reduction Tree

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

reduction_tree_min waveform

6. AXI-Stream Parallel to Serial Converter

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

parallel_to_serial waveform

7. Down Counter (Chainable)

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

down_counter waveform

8. UART RX

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

uart_rx waveform

9. UART TX

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

uart_tx waveform

10. UART Echo (RX + TX) System

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

uart_echo waveform

11. FIR Filter [Naive RTL]

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

fir_filter waveform

12. System: 100-tap FIR Filter via UART [Python filter]

Run results

• Simulation: passed, RTL2GDS: passed

• Artifacts : VCD, SVG, GDS, GDS Logs

Layout Reports

Routing, Placement, Worst path

Waveform (0-10 ns)

sys_fir_filter waveform