Intro to Digital Design - An End-to-End Approach

This is a five-week course, with 30 hours of lectures. We expect the following prior knowledge:

  • Converting a number between decimal, binary and hexadecimal representations material to refresh

  • Basic knowledge of logical operations (AND, OR, NAND, XOR) and truth tables material to refresh

  • Familiarity with any programming language (Python, C, etc.)

Why take this course?

This course is meant to give you a first taste of the art and craft of digital design. Along the way, you will experience the joy of designing real digital circuits and the challenge of making them work.

It is the first step in your journey towards more advanced courses at the university, bigger projects, and eventually the many career paths in one of today’s most exciting and in-demand areas of technology.

8-bit ripple carry adder circuit in 7nm (ASAP7) visualized in 3D. Drag to rotate, scroll to zoom.

Learning Outcomes

The following will be taught through examples (listed here) of increasing complexity, inspired by real digital systems.

Digital Design Concepts

  • Decomposing boolean functions into gates

  • Combinational and sequential elements

  • Finite-state machines

  • AXI-Stream protocol - ready/valid handshake

  • UART protocol - make your circuit talk to your PC

  • Setup time, hold time, critical path, retiming

SystemVerilog for Design

  • Parametrization, hierarchical design

  • always_ff, always_comb, logic

  • generate for, if, case, function, packed arrays

  • 3-process coding style for FSMs

  • Wrapping SystemVerilog in old Verilog

SystemVerilog for Verification

  • Basic testbenches, function, task, queues

  • Randomizing with constraints

  • Transactional testbenches: simple driver/monitor, basic OOP

Keywords & Features of SystemVerilog Avoided in this Course

reg, wire, assign, always, unpacked arrays

SystemVerilog/Verilog is one of the most complex languages ever, with a lot of historical baggage and countless footguns. To avoid wasting our limited time debating those, we will avoid the above. However, I will create a page here explaining each of their uses in detail for the sake of completeness.

Final Projects

  • FIR Filter on FPGA to extract bass/treble from your favorite song

    • A worked example gradually built through our lectures and discussions.

    • We will NOT teach the mathematics of calculating the filter coefficients. Here is our Python file to generate them. We will teach you how such filters work and how to implement them as a circuit.

    • You can listen to the audio before and after applying our 4-bit-quantized, 100-tap low-pass filter (see filter characteristics) with a cutoff of 250 Hz here:

Original music Bass only (250 Hz cutoff)

  • A fully-parallel neural network accelerator on FPGA to classify handwritten numbers

    • You will gradually build this as a series of guided assignments.

    • Week 2: Simple fixed-point quantization and ReLU

    • Week 3: Adder Tree, Vector Multiply-Adder

    • Week 4: Fully-parallel dense layer, neural network, AXI-Stream

    • Week 5: Full system on FPGA with UART RX & TX, plus Python serial to send/receive inputs/outputs

Course Material

Pages

External Links