Syllabus: CSE140 SS1’26

This five-week course introduces digital design by taking circuits from SystemVerilog to simulation, ASIC layout (transistors), and FPGA implementations that talk to your computer. Students build increasingly realistic designs, ending with a neural-network accelerator and an FIR filter for music that communicate via UART.

Course Logistics

  • Instructional Team: Abarajithan G (Instructor), Zhenghua Ma (TA), Sriharsha Kavuri (Tutor) & Aarav Vidhawan (Tutor).

  • Lectures: Tuesdays & Thursdays, 11:00 a.m. - 1:50 p.m., COA - Coalition Building, Room B26.

  • Discussion: Fridays, 3:00 p.m. - 4:50 p.m., COA - Coalition Building, Room 123.

  • Expected workload 16 hours outside class per week. That is 3.2 extra hours per weekday on your own.

  • Office hours:

    • Zhenghua: 2:00 p.m. to 3:00 p.m on Wednesdays & Fridays Zoom link. Since the Friday, 3rd of July is a holiday, that session is moved to Thursday, 2nd of July 07:00 p.m. to 08:00 p.m.

    • Aarav, Harsha: 2:00 p.m. - 3:00 p.m. on Mondays starting on July 6th. Zoom link

    • Abarajithan: 2:00 p.m. - 2:30 p.m. on Tuesdays & Thursdays (after the lecture).

  • Midterm exam: Friday, July 17, 3:00 p.m. - 3:45 p.m., COA - Coalition Building, Room 123. Conducted during discussion session.

  • Final exam: Saturday, August 1, 11:30 a.m. - 2:26 p.m., COA - Coalition Building, Room B26.

  • Students with OSD Accommodations: Midterm at 2:00 pm on Friday, July 17 at Triton Testing Center. Schedule 3 days in advance here. Finals at 11:30 am on August 1 at Triton Testing Center.

Where things live:

Prerequisites: CSE 30 or ECE 30

  • Binary/hex/decimal conversion. [refresher]

  • Basic logic operations and truth tables [refresher]

  • Familiarity with any programming language

Weekly Outcomes, Topics, and Assignments

Week

Learning outcome

Topics and major assignment

1

Understand the digital design flow from Verilog to gates and transistors.

ASIC vs FPGA, layout, standard cells, Boolean functions, gates, testbenches, Docker/FPGA setup.

Assignment 1: decompose Boolean functions, write/simulate SystemVerilog, generate layout, inspect transistors.

2

Design combinational circuits in SystemVerilog.

Adders, muxes, ALUs, encoders, decoders, functions, LUTs.

Assignment 2: build relu(quant(x)) and decompose mux, encoder, decoder, and ReLU logic.

3

Build and debug sequential and parameterized circuits.

Clocks, flip-flops, registers, counters, reduction trees, setup/hold time, critical path.

Assignment 3: build an adder tree, constant-vector MAC, and ReLU-quantized MAC.

4

Integrate streaming, FSM, and UART designs.

AXI-Stream ready/valid, FSMs, UART TX/RX, FPGA serial loopback.

Assignment 4: build dense layers, a dense neural network, and a UART-integrated MNIST system.

5

Create end-to-end digital systems.

FIR filters, retiming, UART RX + FIR + UART TX, Python audio/file I/O.

Extra credit: optimize the end-to-end FPGA systems.

Materials and Support

Class Format and Participation

Class sessions mix short lectures, live code/design prediction, visual simulations, 3D chip exploration, group design time, and low-stakes questions. In a three-hour session, you may expect concept-building, group design/debugging, and integration or reflection, with pauses about every 30 minutes for discussion or problem-solving.

Participation means answering all in-class quizzes, discussing designs with classmates, seeking help early, contributing to Discord, and annotating or responding during lecture. Our classroom will be collaborative: learn each other’s names, work with new peers, discuss your reasoning, and help each other improve.

Grading

Weight

Component

10% each

Assignments (4)

15%

Midterm exam, in person and paper-based

40%

Final exam, in person and paper-based

5%

In-class quiz correctness

100%

Total

-2%

For each missed session (if any in-class quiz was not answered)

+0.5%

Per unused late day

up to +5%

Meaningful participation in Discord & FeedbackFruits with peers

up to +5%

FIR Filter Resource Optimization

up to +10%

Neural Network Resource Optimization

Programming assignments are auto-graded with released and hidden testbenches. Strong work is correct, readable, tested, parameterized where appropriate, and written in the SystemVerilog style taught in class. The paper-based exam will include code closely related to the assignments. Bonus points and missed session penalties are added/subtracted as percentage points to your final score percentage. What counts as “meaningful participation” is up to the discretion of the instructor alone.

Key Policies:

  • Attendance is mandatory for all lectures and discussions:

    • Summer courses are fast-paced, and I don’t want you to fall behind.

    • Each session has 2–3 easy multiple-choice quizzes; to be counted present, you must answer all of them, regardless of correctness.

    • Each missed session has a penalty. You may recover the penalty for at most two missed sessions by printing the slides from the missed session, annotating the printed slides by hand sufficiently based on the recording, and submitting to us before the following lecture.

    • We may offer a quiz at the end of the course to help you make up for the correctness (not attendance) of the in-class quiz on the missed days.

  • Letter grades: A+ (top 5% of students ranked by the total including bonus points), A >=93, A- >=90, B+ >=87, B >=83, B- >=80, C+ >=77, C >=73, C- >=70, D >=60, F otherwise; Ranges may only move in students’ favor.

  • Late work:

    • A total of four 24-hour late days for the entire course with no exceptions. Any fraction of 24 hours counts as one late day.

    • We recommend saving them, in case you encounter a true emergency, and also because you get credit for unused late days.

    • 10 percentage points deducted on the assignment’s grade per late day after you exhaust late days.

  • Exam logistics:

    • The midterm and final are in-person, paper-based, and closed-book;

    • If a valid emergency prevents you from taking an exam (midterm or final), contact the instructor as soon as possible through the Dean of your college. An equivalent oral exam may be arranged.

    • If you miss the final exam for a valid emergency and are eligible under UCSD’s Incomplete policy, your grade may first be submitted as Incomplete due to time constraints, and will be updated later with the oral exam results.

  • Assignments: released Tuesday on that week’s material, due the following Tuesday at 10:00 a.m.

  • Collaboration & Plagiarism:

    • Studying in groups and discussing concepts & examples with peers are highly encouraged.

    • We have a zero-tolerance policy for sharing your solution with anyone but the staff and copying from classmates, past students, online code, or AI tools.

    • We check for plagiarism across all your assignments at the end of the course. Any such case where we have high-confidence results will result in an F for the course for all parties involved and academic-integrity referrals. Check UCSD Policy.

    • If you’re unsure whether something is allowed, ask first in the policy channel @Discord.

  • Regrades: raise requests through Gradescope with detailed explanation within the days allowed on the assignment. No regrades allowed on the final & midterm exams.

  • Policy Changes: Any policy or schedule changes will be announced on Discord. This online syllabus is the current version. Approved UCSD accommodations may modify these policies where required.

AI Use & Academic Integrity

  • The midterm and final exams are paper-based and will test your design skills and knowledge. Therefore, do not use AI to write or debug your code.

  • Avoid IDE-based AI tools entirely. AI may explain general course concepts. It may not generate, complete or debug assignment code; analyze assignment-specific solutions; or produce material submitted for credit. Doing so would result in an F for the course and academic-integrity referrals.

  • Disable AI code completion while working on assignments.

  • Why: As beginners, you need to do the basic designs manually to rewire your brain, so you can use AI more effectively in your jobs later.

Accessibility and Inclusivity

Contact the instructor or the campus accessibility office early to request disability, religious, or other accommodations. Your health and well-being come first. If you’re struggling, reach out to us, and see campus basic needs, counseling (CAPS), and other support resources. Our primary goal is to create an inclusive and welcoming environment for all students.