Exams¶
The real learning in this course happens through the assignments, where you build and test increasingly complex digital designs. The exams extend that work and assess whether you understand it well enough to reason independently, without relying on AI. Both exams are therefore paper-based and use multiple-choice questions, which keep grading manageable so the course staff can devote more time to learning support such as Docker setup, debugging, and FPGA work.
The questions are designed to prevent one mistake from cascading through the rest of the exam while still grouping enough questions around each design context to avoid excessive context switching. Approximately half of each exam focuses on theory and half on SystemVerilog. The midterm covers Weeks 1 and 2 and contains 26 questions, with the best 25 counting toward the score; the cumulative final contains 55 questions, with the best 50 counting. Concepts missed on the midterm may return on the final, so use the midterm results to identify and review gaps rather than relying on random guesses.